The present invention relates to electronic circuits, and, more particularly, to output buffers such as integrated output buffers with slew-rate regulation.
Output buffers are used in many devices for producing an output signal with a desired slew-rate at a certain time and with a certain output voltage-current characteristic. They essentially include a pull-up device and a pull-down device driven by a circuit, and they output a datum with a certain slew-rate and voltage level characteristic when an externally generated enabling signal is active.
A basic diagram of an output buffer is shown in FIG. 3, where an input datum DATO is output (DQ_PAD) with a desired voltage and slew-rate if an enabling signal EN is active. The control circuit (FIG. 4) substantially includes a logic circuit that turns on or forces the buffer into a high impedance state by producing two pull-up and pull down control signals P and N for the pull-up and pull down driving circuits, respectively.
A simple embodiment of the tristate circuit for placing the buffer in a high impedance state is illustrated in FIG. 5. The circuit produces a pair of control signals P and N both equal to the inverted logic signal of the input signal DATO if the enabling signal EN is active or different from each other. This is done independently of the value of the input signal DATO. 
Such circuits, the basic diagram of which is shown in FIG. 6, produce driving signals PGATE and NGATE that switch with a certain variable speed to regulate the slew-rate of the final stage as desired. The slew-rate of the output DQ_PAD depends in general on the load and on the charge/discharge current, which depends upon the size of the transistor of the final stage and from the gate-source voltage applied to the transistors thereof. The slew-rate may be regulated by regulating the gate-source voltage. This is because the load is generally constant and the sizes of the transistors of the final stage are established to have a desired output voltage-current characteristic.
For better comprehension of the technical problem being addressed, a case in which the output of the final stage switches from high to low will now be considered. On the pull-up transistors a voltage PGATE is applied that rapidly reaches the supply value, as illustrated in FIG. 7, and remains at this value indefinitely while the voltage NGATE increases with a certain slope.
The pull-up transistor is immediately turned off while the pull-down transistor turns on slowly. This is so that the output voltage remains at a high value minus a small voltage drop due to the below-threshold current for as long as the pull-down does not leave the below-threshold region.
After a time interval TON (turn-on time) has elapsed, the voltage NGATE overcomes the threshold voltage VTN and the output voltage drops more rapidly. In this phase the output capacitance discharges through a pull-down transistor, as illustrated in FIG. 8, but in a time that depends on the current I flowing therethrough. For this reason, the faster the switching of the signal NGATE is, the faster the current I increases. Thus, the greater the slew-rate of the output DQ_PAD will be and the shorter the response time T_val. With such prior art buffers it is not possible to produce an output datum with a relatively small slew-rate in relatively short response times.
Generally, the buffer should be able to function in different modes depending on the environment in which it works, both in terms of the voltage-current characteristic (e.g., the allowed functioning zones of the voltage-current characteristic for both transitions are shown in FIG. 1, for the case of a PCI 3.3V environment) as well as in terms of output slew-rate (e.g., in a PCI environment the slew-rate must be smaller than that normally required in a TTL environment). The pull-up graph of FIG. 1 corresponds to the equation Ioh+(98.0/Vcc)*(Voutxe2x88x92Vcc)*(Vout+0.4Vcc), where Vcc greater than Vout greater than 0. 7Vcc, and the pull down graph of FIG. 1 corresponds to the equation Iol=(256/Vcc*Vout)*(Vccxe2x88x92Vout), where OV less than Vout less than 0.18Vcc.
Typical values of the slew-rate for a PCI environment under standard load conditions and defined by the specifications are indicated in the following table:
To make the slew-rate of the output compatible with a PCI or TTL environment, the buffer may be designed in a way such that the slew-rate is always equal to the minimum that is ever required. Unfortunately, despite its simplicity, this approach is not convenient because it unduly increases the response time T_VAL of the buffer.
Referring to FIG. 2, the response time T_VAL is the time that elapses from the edge of the clock signal CLK, which determines the instant in which the input datum DATO is read, to the edge of the output DQ_PAD. The response time of prior art buffers is generally the sum of the delay introduced by the logic circuits that form the buffer, of the turn-on time TON of the pull-up or pull-down transistor, and of the time required by the output DQ_PAD for switching from one value to another value with a certain slew-rate.
Because the delay caused by the logic circuits is constant, with the circuit of FIG. 3 the build-up time T_VAL may be reduced only by increasing the speed of variation of the signal that drives the transistor to be turned on. Consequently, a transition of the output DQ_PAD with a slew-rate that may be excessively large for a PCI environment must be determined.
There is a need for an output buffer capable of producing an output datum with a relatively small slew-rate while ensuring an acceptable fast response. Moreover, it would be highly desirable to have an output buffer producing a datum in a certain mode of operation with a slew-rate that may be adjusted at least between two different values, though with response times practically equal or even shorter than the response times of comparable known buffers.
It is an object of the invention to provide a method of driving an output buffer that provides shorter response times than those of prior art buffers with comparable slew-rates.
Another object of the invention is a to provide a method of driving an output buffer that improves response time.
A further object of the invention is to provide an output buffer capable of outputting a datum with a reduced slew-rate and without penalizing the response time.
In contrast to prior art buffers, according to the present invention the slew-rate is controlled by regulating the turn-off and not the turn-on of the pull-up or the pull-down transistors. Considering, for example, a transition from the high state to the low state of the output DQ_PAD, instead of immediately turning off the pull-up transistor and slowly turning on the pull-down transistor, the opposite is done. That is, the pull-down transistor is turned on quickly and the pull-up transistor is turned off slowly.
This approach, despite the increase of power consumption due to the temporary short-circuiting of the supply in the output stage, reduces the time of response for the same slew-rate. This is because T_VAL is no longer limited by the turn-on time TON. The increment of power absorption, due to the short-circuiting of the supply, remains within an acceptable range.
Moreover, it has been observed that the slew-rate of the output switchings may be less sensitive to temperature variations than in prior art buffers because both transistors are turned on during the output switchings. Indeed, temperature variations influence in an opposite manner the pull-up and the pull-down transistors. This is because the output is switched when both transistors are in a conduction state. Thus, the slew-rate becomes less dependent upon temperature.
By having a buffer that may have a faster response than known buffers with the same slew-rate, or a reduced slew-rate with the same response time, it is possible to implement, with few modifications, output buffers with different modes of operation. For example, buffers with a slew-rate that may be set at at least two different values, and a response time equal to or faster than that of comparable prior art buffers of similar fabrication technology may be implemented.
According to one embodiment of the invention, an IC selection signal of the functioning mode, which is applied to the tristate circuit, allows for the selection between at least two different modes of operation of the driving circuits of the pull-up and the pull-down transistors. This determines the switching of the buffer output with one or another slew-rate.